This invention relates to Magnetoresistive Random Access Memories (MRAMs) and other memories where the memory bit has at least two distinct resistance states, and more particularly to sense amplifier circuits for such memories.
Non-volatile memory devices, such as FLASH memories, are extremely important components in electronic systems. FLASH is a major non-volatile memory device in use today. Disadvantages of FLASH memory include high voltage requirements and slow program and erase times. Also, FLASH memory has a poor write endurance of 104-106 cycles before memory failure. In addition, to maintain reasonable data retention, the scaling of the gate oxide is restricted by the tunneling barrier seen by the electrons. Hence, FLASH memory is limited in the dimensions to which it can be scaled.
To overcome these shortcomings, other types of nonvolatile memories are being evaluated. One such device is magnetoresistive RAM (hereinafter referred to as xe2x80x9cMRAMxe2x80x9d). To be commercially practical, however, MRAM must have comparable memory density to current memory technologies, be scalable for future generations, operate at low voltages, have low power consumption, and have competitive read/write speeds.
The resistance of the tunnel junction (TJ) changes value depending on the state of polarization of the magnetic layers above and below the tunnel junction. The resistance changes from a lower resistance value when the magnetic fields are aligned in the same direction to a higher resistance value when they are aligned in opposite directions. The value change may be on the order of thirty percent. Therefore, for a low resistance value of 10K ohms, the high resistance value could be about 13K ohms. A sense amplifier for an MRAM needs to detect this difference in value. Since the nominal value of the resistance has variation due to processing, it is useful to detect the state of a bit by comparing the resistance of the TJ in a bit to a nearby midpoint reference that may be formed as a midpoint of a reference bit in the high state and a reference bit in the low state. It is also important to maintain symmetry to balance the loading from the parasitic resistance and capacitance of the bit lines and the column multiplexing. In U.S. Pat. No. 6,269,040 entitled xe2x80x9cInterconnection network for connecting memory cells to Sense Amplifiersxe2x80x9d by Reohr et al., a resistance of a cell is compared to that of an average resistance between a high and a low reference. In the Reohr et al. circuit, the loading is almost but not fully balanced by sharing reference from two different subarrays to form the midpoint reference. Unfortunately, this solution also requires two sense amplifiers to implement. In addition, for memory arrays that require significant current to charge the bit line capacitance relative to the steady state current signals, such as in an MRAM, a significant percentage of the sensing time may be consumed for bit line charging and equalization.
Most known sense amplifiers have output terminals that are very responsive to movement on the input nodes of the sense amplifier. This responsiveness causes swings on the output nodes as the input nodes are charged to their steady state levels. During swings in voltage, capacitive imbalance may dominate the transient signal, resulting in loss of differential signal and speed of operation.
MRAMs offer the promise of a universal memory that can be high speed and non-volatile. Realizing this promise requires further improvements in speed and memory area efficiency, especially in the sensing speed of stored data values.